Bhavishya G•••

About

On the record

I am currently working as Research Engineer in the European Processor Initiative project at Chalmers University of Technology. My main responsibility in this project is to design and develop a directory based cache coherence controller. I did my PhD at Chalmers University under the supervision of Dr. Sally A. McKee. During my PhD, my research involved designing a reconfigurable L1 data cache, continuing the work on performance counter based statistical power modeling, surveying the power measurement methodologies for power-aware computing, characterizing Intel's hardware transactional memory implementation, and devising a methodology to characterize multicore processors using static and dynamic power modeling. I successfully defended my thesis titled " Measurement, Modeling, and Characterization for Energy-Efficient Computing" on June 16, 2016. Apart from academia, I worked for more than seven years in the industry performing various roles such as FPGA design consultant, embedded systems engineer and post silicon validation engineer across multiple countries (India, Sweden and US).